Instruction Set Architecture

This article focuses on two aspects of emulation : the CPU ( instruction set architecture [ ISA ] emulation ) and devices .

本文专注于仿真的两个方面：CPU（指令集架构[ISA]仿真）和设备。

Emulation also commonly interprets the instructions of the guest VM ( compared to virtualization , where the instruction set architecture of the guests must be the same as the host ) .

仿真还常常解释来宾VM的指令（与虚拟化相比，此处来宾的指令集架构必须与主机相同）。

Research of Java Instruction Set Architecture

Java指令集结构的研究

The features of instruction set architecture and application programs are the key factors to microprocessor architecture .

指令系统和应用程序的特点是决定微处理器体系结构的关键因素。

The platforms we consider include instruction set architecture , operating system , compiler , and programming language .

该平台包括指令集结构，操作系统，编译器和程序设计语言。

Grade . The instruction set architecture , RT level description along with gate level netlist are used in the approach .

该方法要用到处理器的指令集体系结构，RTL级描述和门级网表。

The co verification environment consists of an embedded software debugger and an embedded hardware simulator . It adopts instruction set architecture co simulation model .

该协同验证环境由嵌入式软件调试器和嵌入式硬件模拟器组成，其采用了指令集结构的协同模拟模型。

As software means of code migration , binary translation can convert executable binaries in the absence of its sources from one instruction set architecture to the other .

二进制翻译作为实现代码移植的一种软件手段，能将某一体系结构下的可执行二进制程序在没有其源代码的情况下翻译转换成能在其它体系结构下运行的二进制代码。

Designing Instruction Set Architecture ( ISA ) of the Application Specific Instruction set Processor ( ASIP ) is based on deep understanding of the application algorithm , while understanding of the algorithm depends on analyzing related source code .

专用指令集处理器（ASIP）指令集设计一般都基于对应用算法源码的分析。

The 8 × 8 IDCT algorithm in video image processing was analyzed based on the character of the instruction set architecture and then divided into two stages of matrix multiplication . The multimedia extended instructions of the RISC-DSP processor were applied to realize the IDCT calculation in two steps .

基于RISC-DSP核微处理器的指令集体系结构特点，研究分析了视频图像处理中8×8的IDCT算法，将其分解为两级矩阵乘法运算的结构，并利用RISC-DSP核微处理器的多媒体指令分两步实现。

Computation model , instruction set , architecture and mapping of stream programming model are studied in this dissertation .

本文分别从分片式流处理器的计算模型、指令系统、体系结构、流编程模型映射四个方面开展研究。

Other differences lie in the instruction set , internal architecture , and control signals .

其他差别是在指令系统，内部结构和控制信号方面。

Now that we have studied the instruction set and the architecture of the μ P ( microprocessor ), let 's consider programming it .

既然我们已经学习了微处理器的指令系统及体系结构，那么让我们考虑对其进行编程。

To archive high performance , DVD servo control microprocessor uses RISC like instruction set . Harvard architecture has been used for the servo control microprocessor , having four program and data buses .

为了获得比较高的性能，设计DVD伺服控制微处理器时，采用了具有RISC特征的指令集，程序和数据总线分离的哈佛结构，内部使用了四条程序和数据总线。

Through the environment , the designers can complete the architecture customization quickly , and then generate the instruction set simulator using the architecture description file and operation description file .

通过该环境，设计者可以快速完成处理器架构的定制以及重定向，利用架构描述文件和操作描述文件实现指令集仿真器的快速生成。

According to three aspects : data types , instruction formats , and instruction set , the architecture of an embedded 32 bit RISC microprocessor is introduced in this paper .

本文从数据类型、指令格式与指令集合三个方面介绍一种嵌入式32位RISC微计算机的体系结构。

Traditional Reduced Instruction Set Computer ( RISC ) and Digital Signal Processor ( DSP ) have different application areas due to their different Instruction Set Architecture ( ISA ) and micro-architecture .

传统的精简指令集处理器（RISC）和数字信号处理器（DSP）各自具有不同的指令集结构和微结构特点，适合于不同的应用领域。